1. Field of the Invention
The present invention relates to a signal detection apparatus for detecting original digital information contained in a binary baseband PCM (Pulse Code Modulation) signal transmitted through a communication transmission channel or reproduced from a recording medium.
2. Description of the Prior Art
For detecting signals contained in a binary baseband PCM signal transmitted through a transmission line or reproduced from a recording medium, a method is known in which the original digital signal is detected after partial equalization so as to produce a predetermined specific intersymbol interference (e.g. H. Osawa et al., "Performance Analysis of Partial Response System for Nonreturn-to-Zero Recording", IEEE Transactions on Magnetics, Vol. MAG-22, No. 4, July 1988). A method is also known in which Viterbi decoding, which is a type of maximum-likelihood decoding, is used for detecting the original digital information from a signal which has been subjected to partial response equalization (e.g. H. Kobayashi, "Application of Probablistic Decoding to Digital Magnetic Recording Systems", IBM Journal of Research and Development, Vol. 15, No. January 1971, pp. 64-74). These methods permit the detection of signals at a low bit error rate in comparison to a method in which the original digital information is detected by equalizing and suppressing the intersymbol interference in a channel having substantial intersymbol interference, such as in a magnetic recording channel.
An example in which the above-mentioned detection method as applied to the digital VCR (Video Cassette Recorder) is described in C. Yamamitsu et al., "An Experimental Study on Bit Rate Reduction and High Density Recording for a Home-use Digital VTR", IEEE Transactions on Consumer Electronics, Vol. 34, No. 3, August 1988, pp. 588-596. As described in this reference, a signal reproduced from a detection head and amplified by a detection head amplifier is subjected to partial response equalization in which the intersymbol interference is represented by (1, 0, -1). The poly-nominal expression of this equalization system is 1-D.sup.2, where D denotes a delay of 1 sampling period. It is frequently called partial response Class-IV. The equalized signal is input to a Viterbi decoding circuit. The Viterbi decoding circuit is constituted by an AD converter and other logic circuits. Here, the signal subjected to partial response equalization becomes a 3-level eye pattern signal.
In order to detect the digital information, the clock signal synchronized with the timing of the digital information must be reproduced and supplied to the Viterbi decoding circuit and like components including the AD converter. The clock signal can be easily reproduced from the signal which, being equalized to have no intersymbol interference, exhibits 2-level eye patterns in the normal PLL (Phase Locked Loop) circuit equipped with a phase comparator for comparing a phase of the signal exhibiting 2-level eye patterns at a zero-cross point thereof with a reference clock phase. However, according to the above-mentioned configuration, a problem arises in that, since the signal after equalization exhibits 3-level eye patterns, reproduction of the clock signal is rendered difficult, and as a result, the reproduced clock signal is apt to become unstable.
Further, in the above-mentioned configuration, the partial response equalization must be realized by analog processing. However, realization of an accurate equalization characteristic using analog processing is difficult. Thus, an additional problem arises in that, when the equalization characteristic is not accurate, the bit error rate increases even if Viterbi decoding is carried out.